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[Embeded-SCM Develop] SIN_fashengqi

Description: 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（DSP）技术，通过在 Nios 中软件编程解决 不同的调制方式的实现和选择。系统频率实现 1Hz～20MHz 可调，步进达到了1Hz；完成了调幅、调频、二进制 PSK、二进制 ASK、二进制 FSK 调制和扫频输出的功能。 -2006altera race-based soft-core Nios wide spectrum of sinusoidal signal generator design : Abstract : The use of design-based Nios II embedded processor SOPC technology. Altera Corporation system to the Cyclone FPGA series of digital platform, microprocessor, bus, Digital Frequency Synthesizer, memory and I/O interface hardware concentrated in an FPGA, the use of direct digital frequency synthesis technology and digital modulation waveforms required to achieve the rise, Using FPGA ROM storage of the DDS waveform table, and make full use of on-chip resources, improve the system's accuracy, stability and robustness. Use of new digital signal processing (DSP) technology, Nios through software programming to solve different ways of achieving modulation and choice. Realize the system freq
Platform: | Size: 407552 | Author: 刘斐 | Hits:

[ARM-PowerPC-ColdFire-MIPS] NIOS_new

Description: 基于Altera Cyclone系列FPGA的NIOS II开发板原理图，OrCAD格式-Based on the Altera Cyclone series FPGA-NIOS II development board schematic, OrCAD format
Platform: | Size: 617472 | Author: | Hits:

[VHDL-FPGA-Verilog] Nios

Description: Altera公司开发的用于其FPGA的的Nios软核入门介绍-Developed by Altera for its FPGA of the Nios soft-core entry-Introduction
Platform: | Size: 1537024 | Author: liukun | Hits:

[VHDL-FPGA-Verilog] xd_lcd_comp

Description: 一款240＊128的LCD模块在ALTERA　FPGA　NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference
Platform: | Size: 13312 | Author: 张敏 | Hits:

[VHDL-FPGA-Verilog] c2h_fft_cyclone_ii

Description: 关于用c2h实现fft算法的源代码和说明书 altera-On C2H achieve fft algorithm using the source code and a detailed description of altera
Platform: | Size: 723968 | Author: 梁山皮 | Hits:

[VHDL-FPGA-Verilog] flash_controller

Description: Altera下的FPGA运行Nios处理器的flash控制器-Altera
Platform: | Size: 398336 | Author: lzm | Hits:

[Software Engineering] NiosII_implementation_in_CCD_Camera_for_Pi_of_the_

Description: The concept of the Altera Nios II embedded processor implementation inside Field Programmable Gate Array [FPGA] of the CCD camera for the “Pi of the Sky” experiment is presented. The digital board of the CCD camera, its most important components, current implementation of firmware [VHDL] inside the FPGA and the role of external 8051 microcontroller is briefly described. The main goal of the presented work is to get rid of the external microcontroller and to design new system with Nios II processor built inside FPGA chip. Constraints for implementing the design into the existing camera boards are discussed. New possibilities offered by a larger FPGA for next generation of cameras are considered.-The concept of the Altera Nios II embedded processor implementation inside Field Programmable Gate Array [FPGA] of the CCD camera for the “Pi of the Sky” experiment is presented. The digital board of the CCD camera, its most important components, current implementation of firmware [VHDL] inside the FPGA and the role of external 8051 microcontroller is briefly described. The main goal of the presented work is to get rid of the external microcontroller and to design new system with Nios II processor built inside FPGA chip. Constraints for implementing the design into the existing camera boards are discussed. New possibilities offered by a larger FPGA for next generation of cameras are considered.
Platform: | Size: 1427456 | Author: Francis Wu | Hits:

[VHDL-FPGA-Verilog] tut_nios2_introduction

Description: This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.
Platform: | Size: 116736 | Author: *Roma* | Hits:

[VHDL-FPGA-Verilog] FPGA-DE1-PACMAN

Description: Pacman 4 DE1-FPGA-Board
Platform: | Size: 943104 | Author: bert1970 | Hits:

[VHDL-FPGA-Verilog] MTDB_SYSTEM_CD_V1.0

Description: ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel Daughter Board (MTDB)）扩展开发包。 里为有两个开源的例子 1.MTDB_SD_Card_Audio,从SD卡中读取WAV文件然后通过DA播放，这个对不SD Card的初学者非常的有用，可以知道使用FPGA SPI来读写SD CARD。 2.MTDB_Systhesizer,使用FPGA来做电子琴，要用FPGA来做合成器的看这个。 国内部分地区的网络对TERASIC封杀，原因不明，这个包是使用代理下载的，非常不容易。-ALTERA Nios II Embedded Evaluation Kit development board manufacturers (terasic) to provide multi-media display boards (Terasic Multimedia Touch Panel Daughter Board (MTDB)) the expansion of the development package. Where for example there are two open source 1.MTDB_SD_Card_Audio, from the SD card and then read the WAV file to play through the DA, the SD Card for the beginner is not very useful, we can see that the use of FPGA SPI read and write to SD CARD. 2.MTDB_Systhesizer, the use of FPGA as organ, synthesizer use FPGA to do the look at this. Internal parts of the network to block TERASIC for reasons unknown, the package is downloaded using a proxy, is not easy.
Platform: | Size: 27464704 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] DE2_NIOS_DEVICE_LED

Description: Altera FPGA 上利用nios嵌入式处理器实现USB的通信控制-Altera FPGA embedded processor nios use USB communication to achieve control
Platform: | Size: 4050944 | Author: 秦宜 | Hits:

[VHDL-FPGA-Verilog] Lab2a

Description: C Code for a Nios II to switch led on a board with an FPGA ALTERA
Platform: | Size: 1024 | Author: gios78 | Hits:

[Software Engineering] AlteraArticleContestPapers

Description: 本源码为Altera中国大学生电子设计文章竞赛的历届获奖论文汇编，内容主题涵盖如下4个方面： PLD在通讯、消费类、计算机和工业控制方面的应用 Altera器件、Quartus® II 软件的设计和优化技术 Altera FPGA在数字信号处理中的应用 Nios® II 软处理器在各领域的应用 获奖作品均是是参赛者独立设计的未曾公开发表过的原创性作品，在作品原创性和特色性 、实用性（结合当前的热点应用） 和作品的完整性（有明确的实验或仿真数）上均有很多优势 。 每年的获奖论文共18篇左右。-The source code for Altera Chinese Undergraduate Electronic Design Contest of the previous article, the compilation of award-winning paper, which covers four aspects as follows: PLD in the communications, consumer, computer and industrial control applications Altera devices, Quartus ® II software for design and optimization Altera FPGA technology in digital signal processing applications in the Nios ® II soft processor applications in various fields is the award-winning works were designed by participants independence had not been published original works in the works and the characteristics of originality, practical and (combined with the application of the current hot spots) and the integrity of the work (there are clearly a number of experimental or simulation) have many advantages on. The annual award-winning total of 18 papers around.
Platform: | Size: 26785792 | Author: 成逛 | Hits:

[VHDL-FPGA-Verilog] fpga

Description: 包含5款ALTERA FPGA开发板原理图合集.包含:Cyclone1C20的Nios开发板Cyclone_II_EP2C20_原理图 EP1C3T144 EPM1270F256C5-Contains 5 ALTERA FPGA development board schematics collection. Include: Cyclone1C20 the Nios development board schematics EP1C3T144 EPM1270F256C5 Cyclone_II_EP2C20_
Platform: | Size: 1094656 | Author: 万明 | Hits:

[OS program] webserver_c3

Description: altera fpga embedded processor nios ii design example network
Platform: | Size: 4533248 | Author: 颜鹏珍 | Hits:

[VHDL-FPGA-Verilog] NIOS-II_examples

Description: NIOS 例子程序 Altera的FPGA. NIOS 例子程序 Altera的FPGA. -examples for NIOS in altera
Platform: | Size: 9365504 | Author: wuende | Hits:

[VHDL-FPGA-Verilog] Nios

Description: altera fpga的nios经典教材-altera fpga s classic textbook about nios
Platform: | Size: 3614720 | Author: bentley | Hits:

[VHDL-FPGA-Verilog] an483

Description: The Altera® Triple Speed Ethernet (TSE) data path reference design provides a sample SOPC Builder system using the Altera TSE MegaCore® function with two serial transceivers. This reference design demonstrates the operation of the Altera TSE MegaCore function up to the maximum wire-speed performance in hardware. The design enables you to evaluate the TSE MegaCore function for integration into Altera FPGA designs.-The Altera® Triple Speed Ethernet (TSE) data path reference design provides a sample SOPC Builder system using the Altera TSE MegaCore® function with two serial transceivers. This reference design demonstrates the operation of the Altera TSE MegaCore function up to the maximum wire-speed performance in hardware. The design enables you to evaluate the TSE MegaCore function for integration into Altera FPGA designs.
Platform: | Size: 1467392 | Author: Han | Hits:

[VHDL-FPGA-Verilog] BmpDecoder

Description: 适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码-Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV
Platform: | Size: 2048 | Author: 岳弘达 | Hits:

[Embeded-SCM Develop] ALTERA based NIOS system

Description: 基于ALTERA的NIOS系统的车载显示系统(车载摄像头和TFT显示器)设计源代码(ALTERA based NIOS system on-board display system (on-board camera and TFT display) design source code)
Platform: | Size: 770048 | Author: 大萝卜哥哥 | Hits:
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